Mr Jude Haris
- Research Associate (School of Computing Science)
Biography
Office: G132
School of Computing Science, Sir Alwyn Williams Building, 18 Lilybank Gardens, Glasgow G12 8RZ
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Office: G132
School of Computing Science, Sir Alwyn Williams Building, 18 Lilybank Gardens, Glasgow G12 8RZ
Saha, R. , Haris, J. and Cano, J. (2024) Accelerating PoT Quantization on Edge Devices. In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024, (Accepted for Publication)
Haris, J., Gibson, P., Cano, J. , Bohm Agostini, N. and Kaeli, D. (2023) SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference. Journal of Parallel and Distributed Computing, 173, pp. 140-151. (doi: 10.1016/j.jpdc.2022.11.005)
Haris, J., Gibson, P., Cano, J. , Bohm Agostini, N. and Kaeli, D. (2023) SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference. Journal of Parallel and Distributed Computing, 173, pp. 140-151. (doi: 10.1016/j.jpdc.2022.11.005)
Saha, R. , Haris, J. and Cano, J. (2024) Accelerating PoT Quantization on Edge Devices. In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024, (Accepted for Publication)