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email: r.saha.1@research.gla.ac.uk
Room 219,School of Computing Science, Sir Alwyn Williams Building,
Glasgow G12 8QN
https://orcid.org/0000-0001-9581-0193
Research title: Framework to optimize DNN model inference on FPGA
Currently, I am finding research questions in the field of efficient ML implementation targeting edge FPGA and MCU devices
Saha, R. , Haris, J. and Cano, J. (2024) Accelerating PoT Quantization on Edge Devices. In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024, (Accepted for Publication)
Lu, Y., Gao, C., Saha, R. , Saha, S., McDonald-Maier, K. D. and Zhai, X. (2022) FPGA-Based Dynamic Deep Learning Acceleration for Real-Time Video Analytics. In: Architecture of Computing Systems 35th International Conference, ARCS 2022, Heilbronn, Germany, 13–15 September 2022, ISBN 9783031218675 (doi: 10.1007/978-3-031-21867-5_5)
Saha, R. , Haris, J. and Cano, J. (2024) Accelerating PoT Quantization on Edge Devices. In: 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France, 18-20 Nov 2024, (Accepted for Publication)
Lu, Y., Gao, C., Saha, R. , Saha, S., McDonald-Maier, K. D. and Zhai, X. (2022) FPGA-Based Dynamic Deep Learning Acceleration for Real-Time Video Analytics. In: Architecture of Computing Systems 35th International Conference, ARCS 2022, Heilbronn, Germany, 13–15 September 2022, ISBN 9783031218675 (doi: 10.1007/978-3-031-21867-5_5)
