DESIGN EID
Training researchers in III-V semiconductors
CMOS is the dominant commercial process technology for the fabrication of integrated circuits. Developed in 1960, CMOS processes originally employed metal as the gate conductor. Today, the gates are made from polysilicon. There is also a shift towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. Specifically, there is growing interest in the integration of III-V materials and other complex semiconductors that have advantages over silicon. The EU-funded DESIGN-EID project will address the technological challenge by investigating the impact of defects on electronic and photonic device performance. It will train three early stage researchers to bridge the gap between predictive simulations, experimental materials and device development.
Objective
In semiconductor technology and applications today, we are increasingly observing a shift from the pure silicon CMOS technology towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. In particular, there is a great interest in the heterogeneous and monolithic integration of III-V materials and other complex semiconductors, such as III-Nitrides and SiC on Si substrate. However, the direct growth of III-V materials on silicon inevitably will lead to crystal defects that significantly decreases performance of novel devices.
To overcome this main technological challenge and to make this new technology financially viable, the most cost-effective and time-effective approach is to combine experimental and simulation work, which indeed is the main aim on this project – DESING-EID. This will be achieved by addressing the following objectives.
The first objective of DESIGN-EID is to train three young ESRs who will bridge the gap between predictive simulations, experimental materials and device development by developing simulation tools for prediction of crystal growth as a function of process conditions. Secondly, completely eliminating defects in compound semiconductors is likely not achievable, therefore a simulation framework providing an accurate evaluation of their impact on device performance will be essential for designing devices and materials minimizing their impact. Furthermore, semiconductor defects in semiconductors may be exploited for their unique electronic properties if their presence and properties are controlled. For example, vacancies might be used to implement Qu-bits, whereas extended defects, such as dislocations, can provide unique transport properties. Hence, the last objective of the DESIGN-EID project focuses on experimental control and accurate simulation of the impact of defects on electronic and photonic device performance.
