Course Catalogue

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This course describes the technologies behind current industrial microelectronic packaging, including the properties of the physical materials typically used. Electronic components and their packaging are the building blocks for a vast variety of equipment. Microelectronic packaging is defined as interconnection, powering, cooling, and protecting semiconductor chips for reliable systems. It is a key enabling technology with continuing enhancements, evaluation of building blocks and achieving the requirements for reducing the size, cost, performance, quality, and reliability at the system and product level. This course includes packaging processes such as direct flip-chip attached to organic boards, the ability to increase wiring in the organic board away from expensive drilled technology by the direct deposition of thin organic and metal films, the achievement of reliability without hermeticity previously achieved only in ceramic packaging, and the potential integration of all passive components within the interconnect board.

Course will be delivered continuously in the traditional manner at UESTC.

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75% final written examination

25% Presentations based on individual and group research, preparing report on the titles, which are given below:

■ The Development of Semiconductor Technologies in the Electronic Industry (shifted from bipolar to CMOS) and Thin Film Transistors (TFTs) and their Tremendous Development

■ Microelectronics Packaging Market for the single chip packaging (SCP) and Multi-chip package - Global Industry analysis, Material, Size, Share, and their Growth.

■ The past, present and future research progress on bonding wire for microelectronic packaging and the contribution of Interconnection Technologies regarding electrically, optically, thermally, chemically, and mechanically in the Integrated Circuits.

■ Microelectronics Packaging design (such as, electrical design, thermomechanical design, cooling, materials and their processes, testing and reliability etc.) using suitable software.

Reassessments are normally available for all courses, except those which contribute to the Honours classification. For non-Honours courses, students are offered reassessment in all or any of the components of assessment if the satisfactory (threshold) grade for the overall course is not achieved at the first attempt. This is normally grade D3 for undergraduate students and grade C3 for postgraduate students. Exceptionally it may not be possible to offer reassessment of some coursework items, in which case the mark achieved at the first attempt will be counted towards the final course grade. Any such exceptions for this course are described below.

Due to the nature of the coursework and sequencing of courses, it is not possible to reassess the coursework project and laboratory.

The initial grade on coursework project and laboratory will be used when calculating the resit grade.

This Course will

i) introduce foundational knowledge of packaging materials and processing techniques used in the microelectronics packaging industry,

ii) develop students skills for designing microelectronics packaging,

iii) understand and apply fabrication processes,

iv) evaluate the application of system packaging (wafer to complete system),

v) introduce advanced thermal management technologies,

vi) design microelectronics packaging using suitable software.

By the end of this course students will be able to:

■ understand the properties of common packaging materials and technologies, and assess the appropriateness of these for specific packaging requirements (electrical, thermal and mechanical);

■ apply major challenges technologies of microsystem packages, such as microelectronics, photonics, MEMS and RF wireless devices, system engineering, and system packages.

■ Understand microelectronics packaging materials, such as underfill/mold compounds, solder, thermal interface materials and substrates etc.

■ evaluate qualitatively and quantitatively the effectiveness of different packaging technologies and challenges;

■ discuss the relationship between silicon die processing and die packaging, including the requirements associated with low- dielectrics, die thinning, and die interconnect;

■ apply and evaluate the benefits and restrictions associated with modern system-on-package technologies (such as SOC/SIP/SOP and WLP);

■ design appropriate packaging for industrially relevant electrical, mechanical and thermal requirements.

Students must attend the degree examination and submit at least 75% by weight of the other components of the course's summative assessment.

Students should attend at least 75% of the timetabled classes of the course.

Students must attend to the laboratory classes at given specific timetable.

Note that these are minimum requirements: good students will achieve far higher participation/submission rates. Any student who misses an assessment or a significant number of classes because of illness or other good cause should report this by completing a MyCampus absence report.