Application and Design of Digital Logic 3 (UESTC) UESTC3034
- Academic Session: 2024-25
- School: School of Engineering
- Credits: 18
- Level: Level 3 (SCQF level 9)
- Typically Offered: Semester 1
- Available to Visiting Students: No
- Collaborative Online International Learning: No
Short Description
This course introduces the design methods of digital circuits and system, leading from Logic Algebra, basic gates, functional modules to complex circuit (for example, CPU) based on FPGA chip. A range of examples are carried out in detail, as well as Hardware Description Language (HDL) and Electronic Design Automation (EDA) tools for Very Large-Scale Integrated Chip (VLSI) design.
Timetable
Course will be delivered continuously in the traditional manner at UESTC.
Requirements of Entry
Mandatory Entry Requirements
None.
Recommended Entry Requirements
None.
Excluded Courses
None.
Co-requisites
None.
Assessment
Assessment
75% Written Exam: Closed-book final exam
5% Set Exercises
20% Project:
5% project design report
10% project output
5% Oral Assessment & Presentation
Main Assessment In: December
Are reassessment opportunities available for all summative assessments? No
Due to the nature of the coursework, only the final exam can be reassessed.
Course Aims
The aims of this course are to:
■ develop the skills in the design of simple digital circuits by manual,
■ develop the skills in the design of complex digital circuits by HDL and EDA tools,
■ provide a range of techniques in RISC CPU design, including the ISA, the datapath and the controller.
Intended Learning Outcomes of Course
By the end of this course students will be able to:
■ Explain the fundamentals of digital circuits and digital computer systems.
■ Solve the standard problems related to Boolean algebra.
■ Critically analyse the performance of a digital circuit.
■ Design a typical digital circuit with given constraints.
■ Develop a digital circuit or system using appropriate EDA tools.
Minimum Requirement for Award of Credits
Students must submit at least 75% by weight of the 3 components of the course's summative assessment.
Students must attend the timetabled laboratory classes.